Read tracking refers to providing read signals for a memory cell based on corresponding tracking read signals that are designed to ensure the read signals have sufficient margins for a successful read operation under various conditions. A weakest memory cell refers to a memory cell having the worst read margin among a plurality of memory cells, such as a plurality of memory cells in a memory macro. In various approaches, a signal value of the weakest cell is estimated based on a statistical value of a corresponding signal of the plurality of memory cells, such as a −3σ, a −4σ, a −5σ or a −6σ, etc. Tracking signals are then generated to provide signals for the weakest cell of the plurality of cells. Write tracking operates in a similar way as reading, except for write signals.
In some approaches, after signal values of the weakest cell are identified based on the corresponding statistical values, a delay circuitry built on logic devices is provided to generate signals for the memory cells based on the identified signal values of the weakest cell. Logic devices, however, do not correlate well with memory cells across different manufacturing process, voltage, and temperature (PVT) conditions or corners. As a result, additional delay margins are added for the delay circuitry to cover the worst conditions of the various PVT corners, which results in a longer operational cycle time for the memory macro. Logic circuitry for the additional delay margins also takes up additional layout space, resulting in an increased area for the chip embodying the memory macro.
Like reference symbols in the various drawings indicate like elements.